1 tm hs-303rh-t radiation hardened cmos dual spdt analog switch intersil s satellite applications flow tm (saf) devices are fully tested and guaranteed to 100krad total dose. these qml class t devices are processed to a standard ?w intended to meet the cost and shorter lead-time needs of large v olume satellite manufacturers, while maintaining a high level of reliability. the hs-303rh-t analog switch is a monolithic device f abricated using radiation hardened cmos technology and the intersil dielectric isolation process for latch-up free operation. improved total dose hardness is obtained by layout (thin oxide tabs extending to a channel stop) and processing (hardened gate oxide). this switch offers low- resistance switching performance for analog voltages up to the supply rails. ?n resistance is low and stays reasonably constant over the full range of operating voltage and current. ?n resistance also stays reasonably constant when e xposed to radiation, being typically 30 ? pre-rad and 35 ? post 100krad(si). break-before-make switching is controlled by 5v digital inputs. speci?ations speci?ations for rad hard qml devices are controlled by the defense supply center in columbus (dscc). the smd n umbers listed below must be used when ordering. detailed electrical speci?ations for the hs-303rh-t are contained in smd 5962-95813. a ?ot-link is provided from our website for downloading . intersil s quality management plan (qm plan), listing all class t screening operations, is available on our website. features qml class t, per mil-prf-38535 radiation performance - gamma dose ( ) 1 x 10 5 rad(si) no latch-up, dielectrically isolated device islands pin for pin compatible with intersil hi-303 series analog switches analog signal range 15v ? ow leakage . . . . . . . . . . . . . . . . 100na (max, post rad) ?ow r on . . . . . . . . . . . . . . . . . . . . . . 60 ? (max, post rad) ? ow operating power . . . . . . . . . . 100 a (max, post rad) pinouts hs1-303rh-t (sbdip), cdip2-t14 top view hs9-303rh-t (flatpack) cdfp3-f14 top view ordering information ordering number part number temp. range ( o c) 5962r9581301tcc hs1-303rh-t -55 to 125 5962r9581301txc hs9-303rh-t -55 to 125 note: minimum order quantity for -t is 150 units through distribution, or 450 units direct. nc gnd v+ v- 1 2 3 4 5 6 7 14 13 12 11 10 9 8 in1 s3 d3 d1 s4 d4 d2 in2 s2 s1 nc gnd in1 s3 d3 d1 s1 v+ v- s4 d4 d2 in2 s2 14 13 12 11 10 9 8 2 3 4 5 6 7 1 data sheet november 2001 file number 4602.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ?intersil americas inc. 2001. all rights reserved satellite applications flow (saf) is a trademark of intersil americas inc.
2 all intersil products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation s quality certi?ations can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft w are and/or speci?ations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. f or information regarding intersil corporation and its products, see www.intersil.com functional diagram die characteristics die dimensions: (2130 m x 1930 m x 279 m 25.4 m) 84 x 76 x 11mils 1mil metallization: t ype: al thickness: 12.5k ? 2k ? substrate potential: unbiased (di) ba ckside finish: gold p assivation: t ype: silox (s i o 2 ) thickness: 8k ? 1k ? w orst case current density: < 2.0e5 a/cm 2 transistor count: 76 process: metal gate cmos, dielectric isolation metallization mask layout hs-303rh-t n p in d sbdip truth table logic sw1and sw2 sw3 and sw4 0 off on 1on off d3 d1 s1 in1 nc gnd v- d4 d2 s2 in2 s3 v+ s4
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